1. Field of the Invention
The present invention relates to a semiconductor memory device having a layered bit line structure, and in particular, to a layered bit line structure which uses a twist structure and which is used in, for example, static semiconductor memories.
2. Description of the Related Art
The capacity ratio of bit line to a memory cell is an important parameter for read circuits for semiconductor memory devices. The capacity of the bit lines depends on the structure of memory cells, a material for the bit lines, process parameters, and the number of memory cells connected to one bit line. The reduced size of elements reduces the bit line capacitance per memory capacity bit, enabling an increase in the number of memory cells connected to one bit line. However, an increase in the number of memory cells cannot be simply achieved but must be traded off with a decrease in memory capacity, an increase in noise amount, and the like. On the other hand, cell current has been decreasing consistently with cell size, whereas a higher performance, particularly an increased read speed has been requested. The amount of time from a rise in word line voltage until sense start depends on cell current magnitude, bit line capacitance, and bit line resistance. With no measures taken, the required performance cannot be achieved since the decrease amount of capacity of the bit lines themselves is much smaller than the decrease amount of cell current.
In a memory cell circuit adopting a differential reading scheme of increasing the number of pieces into which a bit line is divided and using a differential sense amplifier to sense and amplify a micro-potential, the cell current is generally small and the above phenomenon is thus marked.
With the cell current reduced, the ability to similarly reduce bit line capacitance and resistance enables the same operation speed as that at a larger cell current to be achieved. In this case, an increase in chip size can be prevented by employing a layered bit line structure to reduce the bit line capacitance and resistance, while preventing an increase in the numbers of sense amplifiers and column decoders. The layered bit line structure is composed of a global bit line pair and a plurality of local bit line pairs. A plurality of basic cell blocks are connected to the global bit line pair. A set of local bit line pairs is connected to each basic cell block. A plurality of memory cells are provided in each basic cell block. A plurality of word lines select one of the plurality of memory cells in each basic cell block. The data in the selected memory cell is read to the corresponding local bit line pair. Moreover, one of the plurality of local bit line pairs is selected and connected to the global bit line pair.
Coupling capacitances are present between the global bit line pair and the plurality of local bit lines. Consequently, the local bit line pair connected to the global bit line pair for data sensing is affected by the remaining local bit line pairs which are not subjected to data sensing. This results in noise in the local bit line pair that is subjected to data sensing. The noise reduces the potential difference between the paired local bit lines that are subjected to data sensing. In this case, since the time to start a sense timing is predetermined, sense margin decreases to prevent correct data from being read.
Jpn. Pat. Appln. KOKAI Publication Nos. 2002-100187 and 8-236714, U.S. Pat. No. 5,815,428, and the like disclose a bit line one-side reading scheme that allows a larger cell current to flow. This scheme adopts a layered bit line structure and a structure in which one of the paired global bit lines also serves as a local bit line. In this case, the global and local bit lines cross each other (the lines are twisted).